In one form of high density interconnect (HDI) circuit module, an adhesive-coated polymer film overlay having via openings covers a substrate which can support integrated circuit chips in chip wells. The polymer film provides an insulated layer upon which is deposited a metallization pattern for interconnection of substrate metallization and/or individual circuit chips through the vias. Methods for performing an HDI process using overlays are further described in Eichelberger et al., U.S. Pat. No. 4,783,695, issued Nov. 8, 1988, and in Eichelberger et al., U.S. Pat. No. 4,933,042, issued Jun. 12, 1990. Generally a plurality of polymer film overlays and metallization patterns are used.
In another form of circuit module fabrication, as described by Cole et al., U.S. Pat. No. 5,527,741, issued Jun. 18, 1996, a method for fabricating a circuit module includes using a flexible interconnect layer having a metallized base insulative layer and an outer insulative layer. At least one circuit chip having chip pads is attached to the base insulative layer and vias are formed in the outer and base insulative layers to expose selected portions of the base insulative layer metallization and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer extending through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the base insulative layer metallization.
Fabrication of thin film resistors, capacitors, and inductors is described in The Handbook of Thin Film Technology, chs. 18 and 19 (Maissel and Glang eds., McGraw-Hill Book Company 1970, 1983 Reissue).
Commonly assigned Wojnarowski et al., "Thin Film Resistors on Organic Surfaces," U.S. Pat. No. 5,675,310, filed Dec. 5, 1994, describes a method for fabricating a thin film resistor comprising: applying a tantalum nitride layer over an organic dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on th tantalum nitride layer. After patterning the metallization layer, the resistance value between the first and second portions of the metallization layer can be determined and compared to a predetermined resistance value, and at least one of the first and second portions can be trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value. Preferably, the tantalum nitride layer comprises a hexagonal closed packed Ta.sub.2 N structure and the dielectric layer comprises a polyimide. Commonly assigned Wojnarowski et al., "Application of Thin Film Electronic Components on Organic and Inorganic Surfaces," U.S. Pat. No. 5,683,928, filed Dec. 5, 1994, describes a method for the manufacture of precision electronic components such as resistors, inductors, and capacitors, for example, on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by changing the physical length of an inductor coil or resistor lead, or by changing the capacitor plate area.
Commonly assigned Saia et al., "Structure and Fabrication Method for Thin Film Capacitors," U.S. Pat. No. 5,736,448, filed Dec. 4, 1995, describes structures and methods of incorporating thin film capacitors on polymer layers such as those in laminated high density interconnect (HDI) multichip modules and in flexible interconnect layers with good adhesion. The capacitors can be fabricated using interconnect metallization (titanium coated with copper coated with titanium) as the lower capacitor plate, amorphous hydrogenated carbon (commonly referred to as diamond-like carbon or DLC) as the capacitor dielectric material, and a sputtered metallization layer as the upper capacitor plate. Good adhesion of DLC to a capacitor plate can be obtained with a thin molybdenum adhesion layer and a pressure graded DLC deposition using an organic precursor including oxygen. The integral capacitors can be fabricated using a fabrication process compatible with conventional HDI and flexible interconnect materials.